toplevel_p2xh Project Status (04/07/2015 - 00:45:48)
Project File: gcdv_update.xise Parser Errors: No Errors
Module Name: toplevel_p2xh Implementation State: Programming File Generated
Target Device: xc3s50a-4vq100
  • Errors:
No Errors
Product Version:ISE 14.4
  • Warnings:
60 Warnings (60 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 571 1,408 40%  
Number of 4 input LUTs 829 1,408 58%  
Number of occupied Slices 578 704 82%  
    Number of Slices containing only related logic 578 578 100%  
    Number of Slices containing unrelated logic 0 578 0%  
Total Number of 4 input LUTs 870 1,408 61%  
    Number used as logic 811      
    Number used as a route-thru 41      
    Number used as Shift registers 18      
Number of bonded IOBs 23 68 33%  
    IOB Master Pads 4      
    IOB Slave Pads 4      
Number of ODDR2s used 4      
Number of BUFGMUXs 4 24 16%  
Number of DCMs 2 2 100%  
Number of MULT18X18SIOs 3 3 100%  
Average Fanout of Non-Clock Nets 2.74      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed 24. Jun 22:42:32 2015060 Warnings (60 new)24 Infos (24 new)
Translation ReportCurrentWed 24. Jun 22:42:47 2015006 Infos (3 new)
Map ReportCurrentWed 24. Jun 22:43:02 2015004 Infos (1 new)
Place and Route ReportCurrentWed 24. Jun 22:43:27 2015000
Power Report     
Post-PAR Static Timing ReportCurrentWed 24. Jun 22:43:35 2015005 Infos (0 new)
Bitgen ReportCurrentWed 24. Jun 22:43:46 2015002 Infos (1 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed 24. Jun 22:43:47 2015
WebTalk Log FileCurrentWed 24. Jun 22:43:56 2015

Date Generated: 06/25/2015 - 21:04:46