Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.4 (WebPack) - P.49d Target Family: Spartan3A and Spartan3AN
OS Platform: NT64 Target Device: xc3s50a
Project ID (random number) a7c1fde7b2ab40ac897190eda6072f4f.1F9D9ED706FE4208B3A250E9E472992A.3 Target Package: vq100
Registration ID 207362003_0_0_611 Target Speed: -4
Date Generated 2015-08-31T23:14:11 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name AMD Sempron(tm) 145 Processor CPU Speed 2812 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Accumulators=3
  • 4-bit updown loadable accumulator=3
Adder Trees=6
  • 4-bit / 4-inputs adder tree=6
Adders/Subtractors=31
  • 11-bit adder=4
  • 11-bit subtractor=1
  • 19-bit adder=3
  • 19-bit subtractor=2
  • 4-bit adder=9
  • 4-bit subtractor=6
  • 5-bit adder=2
  • 9-bit adder=3
  • 9-bit subtractor=1
Comparators=15
  • 10-bit comparator equal=4
  • 11-bit comparator greater=1
  • 19-bit comparator greater=6
  • 2-bit comparator greater=1
  • 4-bit comparator greater=3
Counters=12
  • 10-bit up counter=2
  • 2-bit down counter=1
  • 2-bit up counter=3
  • 3-bit down counter=1
  • 4-bit down counter=1
  • 5-bit up counter=1
  • 6-bit up counter=1
  • 8-bit down counter=2
Decoders=2
  • 1-of-32 decoder=2
FSMs=2 Multiplexers=203
  • 1-bit 2-to-1 multiplexer=150
  • 10-bit 2-to-1 multiplexer=13
  • 10-bit 3-to-1 multiplexer=1
  • 10-bit 4-to-1 multiplexer=2
  • 11-bit 2-to-1 multiplexer=1
  • 16-bit 2-to-1 multiplexer=5
  • 16-bit 5-to-1 multiplexer=1
  • 24-bit 2-to-1 multiplexer=3
  • 28-bit 2-to-1 multiplexer=8
  • 3-bit 2-to-1 multiplexer=2
  • 4-bit 2-to-1 multiplexer=3
  • 6-bit 2-to-1 multiplexer=1
  • 8-bit 2-to-1 multiplexer=7
  • 9-bit 2-to-1 multiplexer=6
Multipliers=5
  • 10x8-bit registered multiplier=1
  • 10x9-bit multiplier=1
  • 11x8-bit registered multiplier=1
  • 8x8-bit registered multiplier=1
  • 9x8-bit registered multiplier=1
RAMs=6
  • 1024x9-bit single-port block Read Only RAM=1
  • 16x10-bit single-port distributed Read Only RAM=3
  • 4x2-bit single-port distributed Read Only RAM=1
  • 512x11-bit single-port block Read Only RAM=1
Registers=1520
  • Flip-Flops=1520
Xors=86
  • 1-bit xor17=2
  • 1-bit xor2=84
MiscellaneousStatistics
  • AGG_BONDED_IO=23
  • AGG_IO=23
  • AGG_SLICE=704
  • NUM_4_INPUT_LUT=1315
  • NUM_BONDED_DIFFMTB=4
  • NUM_BONDED_DIFFSTB=4
  • NUM_BONDED_IBUF=13
  • NUM_BONDED_IOB=2
  • NUM_BUFGMUX=4
  • NUM_CYMUX=194
  • NUM_DCM=2
  • NUM_IOB_FF=9
  • NUM_LUT_RT=69
  • NUM_MULT18X18SIO=3
  • NUM_MULTAND=2
  • NUM_ODDR2_C0=8
  • NUM_RAMB16BWE=2
  • NUM_SHIFT=83
  • NUM_SLICEL=640
  • NUM_SLICEM=64
  • NUM_SLICE_FF=1024
  • NUM_XOR=202
NetStatistics
  • NumNets_Active=1795
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=19
  • NumNodesOfType_Active_BRAMDUMMY=134
  • NumNodesOfType_Active_CLKPIN=690
  • NumNodesOfType_Active_CNTRLPIN=916
  • NumNodesOfType_Active_DOUBLE=3083
  • NumNodesOfType_Active_DUMMY=3774
  • NumNodesOfType_Active_DUMMYBANK=53
  • NumNodesOfType_Active_DUMMYESC=13
  • NumNodesOfType_Active_GLOBAL=75
  • NumNodesOfType_Active_HFULLHEX=28
  • NumNodesOfType_Active_HLONG=9
  • NumNodesOfType_Active_HUNIHEX=124
  • NumNodesOfType_Active_INPUT=4391
  • NumNodesOfType_Active_IOBOUTPUT=22
  • NumNodesOfType_Active_OMUX=1891
  • NumNodesOfType_Active_OUTPUT=1752
  • NumNodesOfType_Active_PREBXBY=1037
  • NumNodesOfType_Active_VFULLHEX=183
  • NumNodesOfType_Active_VLONG=50
  • NumNodesOfType_Active_VUNIHEX=122
  • NumNodesOfType_Vcc_BRAMDUMMY=20
  • NumNodesOfType_Vcc_CNTRLPIN=15
  • NumNodesOfType_Vcc_DUMMY=85
  • NumNodesOfType_Vcc_INPUT=114
  • NumNodesOfType_Vcc_PREBXBY=8
  • NumNodesOfType_Vcc_VCCOUT=60
SiteStatistics
  • IBUF-DIFFMLR=4
  • IBUF-DIFFMTB=2
  • IBUF-DIFFSI_NDT=1
  • IBUF-DIFFSLR=4
  • IBUF-DIFFSTB=1
  • IOB-DIFFMLR=1
  • IOB-DIFFSLR=1
  • SLICEL-SLICEM=288
SiteSummary
  • BUFGMUX=4
  • BUFGMUX_GCLKMUX=4
  • BUFGMUX_GCLK_BUFFER=4
  • DCM=2
  • DCM_DCM=2
  • DIFFMTB=4
  • DIFFMTB_OFF1=4
  • DIFFMTB_OFF2=4
  • DIFFMTB_OFFDDRBLACKBOX=4
  • DIFFMTB_OUTBUF=4
  • DIFFMTB_PAD=4
  • DIFFSTB=4
  • DIFFSTB_DIFFO_IN_USED=4
  • DIFFSTB_OFF1=4
  • DIFFSTB_OUTBUF=4
  • DIFFSTB_PAD=4
  • IBUF=13
  • IBUF_DELAY_ADJ_BBOX=13
  • IBUF_IFF1=9
  • IBUF_INBUF=13
  • IBUF_PAD=13
  • IOB=2
  • IOB_OUTBUF=2
  • IOB_PAD=2
  • MULT18X18SIO=3
  • MULT18X18SIO_MULT18X18SIO=3
  • RAMB16BWE=2
  • RAMB16BWE_RAMB16BWE=2
  • SLICEL=640
  • SLICEL_C1VDD=12
  • SLICEL_C2VDD=9
  • SLICEL_CYMUXF=100
  • SLICEL_CYMUXG=93
  • SLICEL_F=578
  • SLICEL_F5MUX=44
  • SLICEL_F6MUX=2
  • SLICEL_FFX=485
  • SLICEL_FFY=437
  • SLICEL_G=616
  • SLICEL_GAND=2
  • SLICEL_GNDF=33
  • SLICEL_GNDG=32
  • SLICEL_XORF=101
  • SLICEL_XORG=98
  • SLICEM=64
  • SLICEM_CYMUXF=1
  • SLICEM_F=57
  • SLICEM_F5MUX=2
  • SLICEM_F6MUX=2
  • SLICEM_FFX=44
  • SLICEM_FFY=58
  • SLICEM_FMC15_BLACKBOX=5
  • SLICEM_G=64
  • SLICEM_GMC15_BLACKBOX=6
  • SLICEM_GNDF=1
  • SLICEM_WSGEN=62
  • SLICEM_XORF=3
 
Configuration Data
BUFGMUX
  • S=[S_INV:4] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:4]
  • S=[S_INV:4] [S:0]
DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:2]
  • PSEN=[PSEN_INV:0] [PSEN:2]
  • PSINCDEC=[PSINCDEC:2] [PSINCDEC_INV:0]
  • RST=[RST:2] [RST_INV:0]
DCM_DCM
  • CLKDV_DIVIDE=[2:2]
  • CLKIN_DIVIDE_BY_2=[CLKIN_DIVIDE_BY_2:2]
  • CLKOUT_PHASE_SHIFT=[NONE:2]
  • CLK_FEEDBACK=[1X:1] [2X:1]
  • DESKEW_ADJUST=[9:2]
  • DFS_FREQUENCY_MODE=[LOW:2]
  • DLL_FREQUENCY_MODE=[LOW:2]
  • DUTY_CYCLE_CORRECTION=[TRUE:2]
  • FACTORY_JF1=[0XC0:2]
  • FACTORY_JF2=[0X80:2]
  • PSCLK=[PSCLK_INV:0] [PSCLK:2]
  • PSEN=[PSEN_INV:0] [PSEN:2]
  • PSINCDEC=[PSINCDEC:2] [PSINCDEC_INV:0]
  • RST=[RST:2] [RST_INV:0]
  • STARTUP_WAIT=[STARTUP_WAIT:2]
DIFFMTB
  • O1=[O1_INV:4] [O1:0]
  • OCE=[OCE:4] [OCE_INV:0]
  • ODDRIN2=[ODDRIN2:4] [ODDRIN2_INV:0]
  • OTCLK1=[OTCLK1_INV:0] [OTCLK1:4]
  • OTCLK2=[OTCLK2_INV:0] [OTCLK2:4]
  • T1=[T1_INV:0] [T1:4]
DIFFMTB_OFF1
  • CE=[CE:4] [CE_INV:0]
  • CK=[CK:4] [CK_INV:0]
  • D=[D:0] [D_INV:4]
  • LATCH_OR_FF=[FF:4]
  • OFF1_INIT_ATTR=[INIT0:4]
DIFFMTB_OFF2
  • CE=[CE:4] [CE_INV:0]
  • CK=[CK:4] [CK_INV:0]
  • D=[D:4] [D_INV:0]
  • LATCH_OR_FF=[FF:4]
  • OFF2_INIT_ATTR=[INIT0:4]
DIFFMTB_OUTBUF
  • IN=[IN_INV:0] [IN:4]
  • SUSPEND=[3STATE:4]
  • TRI=[TRI_INV:0] [TRI:4]
DIFFMTB_PAD
  • IOATTRBOX=[TMDS_33:4]
DIFFSTB
  • O1=[O1_INV:4] [O1:0]
  • OCE=[OCE:4] [OCE_INV:0]
  • OTCLK1=[OTCLK1_INV:0] [OTCLK1:4]
DIFFSTB_OFF1
  • CE=[CE:4] [CE_INV:0]
  • CK=[CK:4] [CK_INV:0]
  • D=[D:0] [D_INV:4]
  • LATCH_OR_FF=[FF:4]
  • OFF1_INIT_ATTR=[INIT0:4]
DIFFSTB_OUTBUF
  • SUSPEND=[3STATE:4]
DIFFSTB_PAD
  • IOATTRBOX=[TMDS_33:4]
IBUF
  • ICE=[ICE:9] [ICE_INV:0]
  • ICLK1=[ICLK1_INV:0] [ICLK1:9]
IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:13]
  • IBUF_DELAY_VALUE=[DLY0:13]
  • IFD_DELAY_VALUE=[DLY0:4] [DLY5:9]
  • SEL_IN=[SEL_IN:13] [SEL_IN_INV:0]
IBUF_IFF1
  • CE=[CE:9] [CE_INV:0]
  • CK=[CK:9] [CK_INV:0]
  • IFF1_INIT_ATTR=[INIT0:9]
  • LATCH_OR_FF=[FF:9]
IBUF_PAD
  • IOATTRBOX=[LVCMOS33:13]
IOB
  • O1=[O1_INV:0] [O1:2]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:2]
  • SUSPEND=[3STATE:2]
IOB_PAD
  • DRIVEATTRBOX=[12:2]
  • IOATTRBOX=[LVCMOS33:2]
  • SLEW=[SLOW:2]
MULT18X18SIO
  • CEA=[CEA_INV:0] [CEA:3]
  • CEB=[CEB_INV:0] [CEB:3]
  • CEP=[CEP:3] [CEP_INV:0]
  • CLK=[CLK:3] [CLK_INV:0]
  • RSTA=[RSTA:3] [RSTA_INV:0]
  • RSTB=[RSTB:3] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:3]
MULT18X18SIO_MULT18X18SIO
  • AREG=[0:3]
  • BREG=[0:3]
  • B_INPUT=[DIRECT:3]
  • CEA=[CEA_INV:0] [CEA:3]
  • CEB=[CEB_INV:0] [CEB:3]
  • CEP=[CEP:3] [CEP_INV:0]
  • CLK=[CLK:3] [CLK_INV:0]
  • PREG=[0:1] [1:2]
  • PREG_CLKINVERSION=[0:3]
  • RSTA=[RSTA:3] [RSTA_INV:0]
  • RSTB=[RSTB:3] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:3]
RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:2]
  • ENA=[ENA_INV:0] [ENA:2]
  • SSRA=[SSRA_INV:0] [SSRA:2]
  • WEA0=[WEA0:2] [WEA0_INV:0]
  • WEA1=[WEA1:2] [WEA1_INV:0]
  • WEA2=[WEA2:2] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:2]
  • WEB0=[WEB0:0] [WEB0_INV:2]
  • WEB1=[WEB1:0] [WEB1_INV:2]
  • WEB2=[WEB2_INV:2] [WEB2:0]
  • WEB3=[WEB3:0] [WEB3_INV:2]
RAMB16BWE_RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:2]
  • DATA_WIDTH_A=[9:1] [18:1]
  • DATA_WIDTH_B=[0:2]
  • ENA=[ENA_INV:0] [ENA:2]
  • SSRA=[SSRA_INV:0] [SSRA:2]
  • WEA0=[WEA0:2] [WEA0_INV:0]
  • WEA1=[WEA1:2] [WEA1_INV:0]
  • WEA2=[WEA2:2] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:2]
  • WEB0=[WEB0:0] [WEB0_INV:2]
  • WEB1=[WEB1:0] [WEB1_INV:2]
  • WEB2=[WEB2_INV:2] [WEB2:0]
  • WEB3=[WEB3:0] [WEB3_INV:2]
  • WRITE_MODE_A=[WRITE_FIRST:2]
  • WRITE_MODE_B=[WRITE_FIRST:2]
SLICEL
  • BX=[BX_INV:1] [BX:170]
  • BY=[BY:185] [BY_INV:12]
  • CE=[CE:542] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:87]
  • CLK=[CLK:599] [CLK_INV:0]
  • SR=[SR:241] [SR_INV:0]
SLICEL_CYMUXF
  • 0=[0:100] [0_INV:0]
  • 1=[1_INV:0] [1:100]
SLICEL_CYMUXG
  • 0=[0:93] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:44] [S0_INV:0]
SLICEL_F6MUX
  • S0=[S0:2] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:442] [CE_INV:0]
  • CK=[CK:485] [CK_INV:0]
  • D=[D:484] [D_INV:1]
  • FFX_INIT_ATTR=[INIT0:465] [INIT1:20]
  • FFX_SR_ATTR=[SRLOW:483] [SRHIGH:2]
  • LATCH_OR_FF=[FF:485]
  • REV=[REV_INV:0] [REV:29]
  • SR=[SR:205] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:280] [SYNC:205]
SLICEL_FFY
  • CE=[CE:392] [CE_INV:0]
  • CK=[CK:437] [CK_INV:0]
  • D=[D:425] [D_INV:12]
  • FFY_INIT_ATTR=[INIT0:412] [INIT1:25]
  • FFY_SR_ATTR=[SRLOW:435] [SRHIGH:2]
  • LATCH_OR_FF=[FF:437]
  • SR=[SR:147] [SR_INV:0]
  • SYNC_ATTR=[ASYNC:290] [SYNC:147]
SLICEL_XORF
  • 1=[1_INV:0] [1:101]
SLICEM
  • BX=[BX_INV:2] [BX:32]
  • BY=[BY:63] [BY_INV:0]
  • CE=[CE:59] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:4]
  • CLK=[CLK:62] [CLK_INV:0]
  • SHIFTIN=[SHIFTIN_INV:0] [SHIFTIN:3]
  • SR=[SR:62] [SR_INV:0]
SLICEM_CYMUXF
  • 0=[0:1] [0_INV:0]
  • 1=[1_INV:0] [1:1]
SLICEM_F
  • DI=[DI:21] [DI_INV:0]
  • F_ATTR=[SHIFT_REG:21]
  • LUT_OR_MEM=[LUT:36] [RAM:21]
SLICEM_F5MUX
  • S0=[S0:2] [S0_INV:0]
SLICEM_F6MUX
  • S0=[S0:2] [S0_INV:0]
SLICEM_FFX
  • CE=[CE:42] [CE_INV:0]
  • CK=[CK:44] [CK_INV:0]
  • D=[D:42] [D_INV:2]
  • FFX_INIT_ATTR=[INIT0:43] [INIT1:1]
  • FFX_SR_ATTR=[SRLOW:44]
  • LATCH_OR_FF=[FF:44]
  • SYNC_ATTR=[ASYNC:44]
SLICEM_FFY
  • CE=[CE:55] [CE_INV:0]
  • CK=[CK:58] [CK_INV:0]
  • D=[D:58] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:55] [INIT1:3]
  • FFY_SR_ATTR=[SRLOW:58]
  • LATCH_OR_FF=[FF:58]
  • SYNC_ATTR=[ASYNC:58]
SLICEM_G
  • DI=[DI:62] [DI_INV:0]
  • G_ATTR=[SHIFT_REG:62]
  • LUT_OR_MEM=[LUT:2] [RAM:62]
SLICEM_WSGEN
  • CK=[CK:62] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:62]
  • WE=[WE_INV:0] [WE:62]
SLICEM_XORF
  • 1=[1_INV:0] [1:3]
 
Pin Data
BUFGMUX
  • I0=4
  • O=4
  • S=4
BUFGMUX_GCLKMUX
  • I0=4
  • OUT=4
  • S=4
BUFGMUX_GCLK_BUFFER
  • IN=4
  • OUT=4
DCM
  • CLK0=1
  • CLK2X=1
  • CLKFB=2
  • CLKFX=2
  • CLKFX180=1
  • CLKIN=2
  • LOCKED=2
  • PSCLK=2
  • PSEN=2
  • PSINCDEC=2
  • RST=2
  • STATUS2=2
DCM_DCM
  • CLK0=1
  • CLK2X=1
  • CLKFB=2
  • CLKFX=2
  • CLKFX180=1
  • CLKIN=2
  • LOCKED=2
  • PSCLK=2
  • PSEN=2
  • PSINCDEC=2
  • RST=2
  • STATUS2=2
DIFFMTB
  • DIFFO_OUT=4
  • O1=4
  • OCE=4
  • ODDRIN2=4
  • OTCLK1=4
  • OTCLK2=4
  • PAD=4
  • T1=4
DIFFMTB_OFF1
  • CE=4
  • CK=4
  • D=4
  • Q=4
DIFFMTB_OFF2
  • CE=4
  • CK=4
  • D=4
  • Q=4
DIFFMTB_OFFDDRBLACKBOX
  • OFF1=4
  • OFF2=4
  • OFFDDR=4
DIFFMTB_OUTBUF
  • IN=4
  • OUTN=4
  • OUTP=4
  • TRI=4
DIFFMTB_PAD
  • PAD=4
DIFFSTB
  • DIFFO_IN=4
  • O1=4
  • OCE=4
  • ODDROUT1=4
  • OTCLK1=4
  • PAD=4
DIFFSTB_DIFFO_IN_USED
  • 0=4
  • OUT=4
DIFFSTB_OFF1
  • CE=4
  • CK=4
  • D=4
  • Q=4
DIFFSTB_OUTBUF
  • DIFFO_IN=4
  • OUTP=4
DIFFSTB_PAD
  • PAD=4
IBUF
  • I=13
  • ICE=9
  • ICLK1=9
  • IQ1=9
  • PAD=13
IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=13
  • IFD_OUT=9
  • SEL_IN=13
IBUF_IFF1
  • CE=9
  • CK=9
  • D=9
  • Q=9
IBUF_INBUF
  • IN=13
  • OUT=13
IBUF_PAD
  • PAD=13
IOB
  • O1=2
  • PAD=2
IOB_OUTBUF
  • IN=2
  • OUT=2
IOB_PAD
  • PAD=2
MULT18X18SIO
  • A0=3
  • A1=3
  • A10=3
  • A11=3
  • A12=3
  • A13=3
  • A14=3
  • A15=3
  • A16=3
  • A17=3
  • A2=3
  • A3=3
  • A4=3
  • A5=3
  • A6=3
  • A7=3
  • A8=3
  • A9=3
  • B0=3
  • B1=3
  • B10=3
  • B11=3
  • B12=3
  • B13=3
  • B14=3
  • B15=3
  • B16=3
  • B17=3
  • B2=3
  • B3=3
  • B4=3
  • B5=3
  • B6=3
  • B7=3
  • B8=3
  • B9=3
  • CEA=3
  • CEB=3
  • CEP=3
  • CLK=3
  • P0=3
  • P1=3
  • P10=3
  • P11=3
  • P12=3
  • P13=3
  • P14=3
  • P15=3
  • P16=3
  • P17=3
  • P18=2
  • P2=3
  • P3=3
  • P4=3
  • P5=3
  • P6=3
  • P7=3
  • P8=3
  • P9=3
  • RSTA=3
  • RSTB=3
  • RSTP=3
MULT18X18SIO_MULT18X18SIO
  • A0=3
  • A1=3
  • A10=3
  • A11=3
  • A12=3
  • A13=3
  • A14=3
  • A15=3
  • A16=3
  • A17=3
  • A2=3
  • A3=3
  • A4=3
  • A5=3
  • A6=3
  • A7=3
  • A8=3
  • A9=3
  • B0=3
  • B1=3
  • B10=3
  • B11=3
  • B12=3
  • B13=3
  • B14=3
  • B15=3
  • B16=3
  • B17=3
  • B2=3
  • B3=3
  • B4=3
  • B5=3
  • B6=3
  • B7=3
  • B8=3
  • B9=3
  • CEA=3
  • CEB=3
  • CEP=3
  • CLK=3
  • P0=3
  • P1=3
  • P10=3
  • P11=3
  • P12=3
  • P13=3
  • P14=3
  • P15=3
  • P16=3
  • P17=3
  • P18=2
  • P2=3
  • P3=3
  • P4=3
  • P5=3
  • P6=3
  • P7=3
  • P8=3
  • P9=3
  • RSTA=3
  • RSTB=3
  • RSTP=3
RAMB16BWE
  • ADDRA10=2
  • ADDRA11=2
  • ADDRA12=2
  • ADDRA13=2
  • ADDRA3=1
  • ADDRA4=2
  • ADDRA5=2
  • ADDRA6=2
  • ADDRA7=2
  • ADDRA8=2
  • ADDRA9=2
  • CLKA=2
  • DOA0=2
  • DOA1=2
  • DOA10=1
  • DOA2=2
  • DOA3=2
  • DOA4=2
  • DOA5=2
  • DOA6=2
  • DOA7=2
  • DOA8=1
  • DOA9=1
  • DOPA0=1
  • ENA=2
  • SSRA=2
  • WEA0=2
  • WEA1=2
  • WEA2=2
  • WEA3=2
  • WEB0=2
  • WEB1=2
  • WEB2=2
  • WEB3=2
RAMB16BWE_RAMB16BWE
  • ADDRA10=2
  • ADDRA11=2
  • ADDRA12=2
  • ADDRA13=2
  • ADDRA3=1
  • ADDRA4=2
  • ADDRA5=2
  • ADDRA6=2
  • ADDRA7=2
  • ADDRA8=2
  • ADDRA9=2
  • CLKA=2
  • DOA0=2
  • DOA1=2
  • DOA10=1
  • DOA2=2
  • DOA3=2
  • DOA4=2
  • DOA5=2
  • DOA6=2
  • DOA7=2
  • DOA8=1
  • DOA9=1
  • DOPA0=1
  • ENA=2
  • SSRA=2
  • WEA0=2
  • WEA1=2
  • WEA2=2
  • WEA3=2
  • WEB0=2
  • WEB1=2
  • WEB2=2
  • WEB3=2
SLICEL
  • BX=171
  • BY=197
  • CE=542
  • CIN=87
  • CLK=599
  • COUT=93
  • F1=574
  • F2=524
  • F3=393
  • F4=241
  • F5=4
  • FX=1
  • FXINA=2
  • FXINB=2
  • G1=615
  • G2=563
  • G3=446
  • G4=272
  • SR=241
  • X=197
  • XQ=485
  • Y=301
  • YQ=437
SLICEL_C1VDD
  • 1=12
SLICEL_C2VDD
  • 1=9
SLICEL_CYMUXF
  • 0=100
  • 1=100
  • OUT=100
  • S0=100
SLICEL_CYMUXG
  • 0=93
  • 1=93
  • OUT=93
  • S0=93
SLICEL_F
  • A1=574
  • A2=524
  • A3=393
  • A4=241
  • D=578
SLICEL_F5MUX
  • F=43
  • G=44
  • OUT=44
  • S0=44
SLICEL_F6MUX
  • 0=2
  • 1=2
  • OUT=2
  • S0=2
SLICEL_FFX
  • CE=442
  • CK=485
  • D=485
  • Q=485
  • REV=29
  • SR=205
SLICEL_FFY
  • CE=392
  • CK=437
  • D=437
  • Q=437
  • SR=147
SLICEL_G
  • A1=615
  • A2=563
  • A3=446
  • A4=272
  • D=616
SLICEL_GAND
  • 0=2
  • 1=2
  • O=2
SLICEL_GNDF
  • 0=33
SLICEL_GNDG
  • 0=32
SLICEL_XORF
  • 0=101
  • 1=101
  • O=101
SLICEL_XORG
  • 0=98
  • 1=98
  • O=98
SLICEM
  • BX=34
  • BY=63
  • CE=59
  • CIN=4
  • CLK=62
  • F1=52
  • F2=51
  • F3=44
  • F4=31
  • F5=2
  • FX=1
  • FXINA=2
  • FXINB=2
  • G1=58
  • G2=58
  • G3=58
  • G4=57
  • SHIFTIN=3
  • SHIFTOUT=3
  • SR=62
  • X=23
  • XB=3
  • XQ=44
  • Y=1
  • YQ=58
SLICEM_CYMUXF
  • 0=1
  • 1=1
  • OUT=1
  • S0=1
SLICEM_F
  • A1=52
  • A2=51
  • A3=44
  • A4=31
  • D=52
  • DI=21
  • WS=21
SLICEM_F5MUX
  • F=1
  • G=2
  • OUT=2
  • S0=2
SLICEM_F6MUX
  • 0=2
  • 1=2
  • OUT=2
  • S0=2
SLICEM_FFX
  • CE=42
  • CK=44
  • D=44
  • Q=44
SLICEM_FFY
  • CE=55
  • CK=58
  • D=58
  • Q=58
SLICEM_FMC15_BLACKBOX
  • MC15=5
  • WS2=5
SLICEM_G
  • A1=58
  • A2=58
  • A3=58
  • A4=57
  • D=58
  • DI=62
  • WS=62
SLICEM_GMC15_BLACKBOX
  • MC15=6
  • WS2=6
SLICEM_GNDF
  • 0=1
SLICEM_WSGEN
  • CK=62
  • WE=62
  • WSF=21
  • WSG=62
SLICEM_XORF
  • 0=3
  • 1=3
  • O=3
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s50a-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s50a-vq100-4 -timing -logic_opt on -ol high -xe n -t 1 -register_duplication on -cm balanced -ir off -ignore_keep_hierarchy -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s50a-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s50a-vq100-4 -timing -logic_opt on -ol high -xe n -t 1 -register_duplication on -cm balanced -ir off -ignore_keep_hierarchy -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s50a-vq100-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s50a-vq100-4 -timing -logic_opt on -ol high -xe n -t 1 -register_duplication on -cm balanced -ir off -ignore_keep_hierarchy -pr b -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -xe n -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
XSLTProcess 214 168 0 0 0 0 0
_impact 7 7 0 0 0 0 0
arwz 18 18 0 0 0 0 0
bitgen 154 154 0 0 0 0 0
cpldfit 220 220 0 0 0 0 0
hprep6 200 200 0 0 0 0 0
map 196 176 0 0 0 0 0
ngc2edif 1 1 0 0 0 0 0
ngdbuild 422 422 0 0 0 0 0
par 176 166 10 0 0 0 0
taengine 6 6 0 0 0 0 0
trce 166 166 0 0 0 0 0
tsim 205 205 0 0 0 0 0
xst 556 554 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/wizards/arwz/awz_db_dcmadv.htm ( 2 )
 
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000 PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked) PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthOptEffort=High PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2015-02-06T21:51:55
PROP_intWbtProjectID=1F9D9ED706FE4208B3A250E9E472992A PROP_intWbtProjectIteration=3
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxBitgStart_IntDone=true PROP_xilxMapAllowLogicOpt=true
PROP_xilxMapCoverMode=Balanced PROP_xilxMapPackRegInto=For Inputs and Outputs
PROP_xilxMapTimingDrivenPacking=true PROP_xilxSynthRegBalancing=Yes
PROP_xstOptimizeInsPrimtives=true PROP_xst_otherCmdLineOptions=-use_new_parser YES
PROP_AutoTop=true PROP_DevFamily=Spartan3A and Spartan3AN
PROP_MapLogicOptimization=true PROP_MapRegDuplication=On
PROP_DevDevice=xc3s50a PROP_DevFamilyPMName=spartan3a
PROP_MapExtraEffort=Normal PROP_xilxPARextraEffortLevel=Normal
PROP_DevPackage=vq100 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=VHDL
FILE_UCF=1 FILE_VHDL=22
 
Unisim Statistics
XST_UNISIM_SUMMARY
XST_NUM_BUFG=1 XST_NUM_IBUFG=1 XST_NUM_OBUFTDS=4 XST_NUM_ODDR2=4
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_DCM_SP=2 NGDBUILD_NUM_FD=79 NGDBUILD_NUM_FDE=602
NGDBUILD_NUM_FDR=6 NGDBUILD_NUM_FDRE=313 NGDBUILD_NUM_FDRS=2 NGDBUILD_NUM_FDRSE=27
NGDBUILD_NUM_FDSE=4 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=12 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=57 NGDBUILD_NUM_LUT1=65 NGDBUILD_NUM_LUT2=250 NGDBUILD_NUM_LUT2_D=6
NGDBUILD_NUM_LUT2_L=1 NGDBUILD_NUM_LUT3=323 NGDBUILD_NUM_LUT3_D=10 NGDBUILD_NUM_LUT3_L=4
NGDBUILD_NUM_LUT4=442 NGDBUILD_NUM_LUT4_D=58 NGDBUILD_NUM_LUT4_L=32 NGDBUILD_NUM_MULT18X18SIO=3
NGDBUILD_NUM_MULT_AND=2 NGDBUILD_NUM_MUXCY=194 NGDBUILD_NUM_MUXF5=44 NGDBUILD_NUM_MUXF6=3
NGDBUILD_NUM_MUXF7=1 NGDBUILD_NUM_OBUF=2 NGDBUILD_NUM_OBUFTDS=4 NGDBUILD_NUM_ODDR2=4
NGDBUILD_NUM_RAMB16BWE=2 NGDBUILD_NUM_SRLC16E=83 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=202
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_DCM_SP=2 NGDBUILD_NUM_FD=79 NGDBUILD_NUM_FDE=602
NGDBUILD_NUM_FDR=6 NGDBUILD_NUM_FDRE=313 NGDBUILD_NUM_FDRS=2 NGDBUILD_NUM_FDRSE=27
NGDBUILD_NUM_FDSE=4 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=12 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=57 NGDBUILD_NUM_LUT1=65 NGDBUILD_NUM_LUT2=250 NGDBUILD_NUM_LUT2_D=6
NGDBUILD_NUM_LUT2_L=1 NGDBUILD_NUM_LUT3=323 NGDBUILD_NUM_LUT3_D=10 NGDBUILD_NUM_LUT3_L=4
NGDBUILD_NUM_LUT4=442 NGDBUILD_NUM_LUT4_D=58 NGDBUILD_NUM_LUT4_L=32 NGDBUILD_NUM_MULT18X18SIO=3
NGDBUILD_NUM_MULT_AND=2 NGDBUILD_NUM_MUXCY=194 NGDBUILD_NUM_MUXF5=44 NGDBUILD_NUM_MUXF6=3
NGDBUILD_NUM_MUXF7=1 NGDBUILD_NUM_OBUF=2 NGDBUILD_NUM_OBUFTDS=4 NGDBUILD_NUM_ODDR2=4
NGDBUILD_NUM_RAMB16BWE=2 NGDBUILD_NUM_SRLC16E=83 NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=202
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s50a-4-vq100 -top=<design_top> -opt_mode=Speed -opt_level=2
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=100000 -bufg=24
-register_duplication=YES -register_balancing=Yes -move_first_stage=YES -move_last_stage=YES
-optimize_primitives=YES -use_clock_enable=Yes -use_sync_set=Yes -use_sync_reset=Yes
-iob=Auto -equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5